The maximum operating speed of current semiconductor devices is limited by the time delay factor T=RC of metal layers, where the resistance R is from the metal lines and the capacitance C is from the dielectric insulating material surrounding the metal lines. As the minimum feature size on integrated circuits shrinks below 0.18 μm, the metal lines become thinner and more densely packed, resulting in greater resistance in the metal lines and larger inter-metal capacitance, and therefore a longer time delay. By changing to different materials, i.e., higher conductivity material for the metal lines and lower permittivity (low-k) dielectric for the insulating material, device geometry can continue to shrink without adversely impacting the maximum operating speed. This prompted the switch from aluminum and silicon dioxide to copper and low-k dielectrics in the backend process flow for manufacturing many current and future semiconductor devices.
The switch from aluminum/oxide to copper/low-k involves a variety of fundamental changes in the backend manufacturing process flow. Since it is difficult to etch copper, new approaches such as “damascene” or “dual damascene” processing are required. Copper damascene/dual-damascene is a process where vias and trenches are etched into the insulating material. Copper is then filled into the vias and trenches and sanded back using a process such as chemical mechanical polishing (CMP), so the conducting materials are only left in the vias and trenches. Among the many challenges presented by this process, etching trenches or vias in low-k dielectrics can be tricky due to the more complicated chemical composition of the dielectric material and the many different kinds of low-k dielectric materials available. The etch chemistry for etching a low-k dielectric material may have to be tailored to match up with the amount of carbon, hydrogen, silicon, fluorine and oxygen in the material.
The ratio of the rate of etching a low-k dielectric layer to the rate of etching one of adjacent layers of other materials is called etching selectivity. A photoresist layer is typically used to mask the low-k dielectric layer during the dielectric etching process. Compared with traditional dielectric etching processes, selectively etching low-k dielectric materials requires more precise tuning of the process chemistry and process parameters because like photoresist, many low-k dielectric materials also contain some carbon and hydrogen, making it harder to achieve good selectivity. Poor selectivity to photoresist has been found to contribute to striations or rough surfaces on the sidewalls of etched micro-features. Striations are not desirable for optimum performance of the integrated circuits because the rough feature surfaces make metallization difficult. Poor selectivity to photoresist also contributes to loss of critical dimensions (CD), which has become less and less tolerable with the shrink of feature sizes.